Programm
| 09:30 | - | 10:30 | Anreise/Empfang |
| 10:30 | - | 10:45 | Eröffnung |
| 10:45 | - | 11:30 | Next generation Prototyping – a hybrid approach
Keynote 1 | Uwe Grüner |
| 11:30 | - | 12:00 | GPZV/GINKO Kurzpräsentationen |
| 12:00 | - | 13:15 | Mittagspause |
| 13:15 | - | 15:15 | Session 1 |
| 13:15 | - | 13:45 | Verfahren zur Assertion basierten Verifikation bei der High-Level-Synthese | Christian Schott, Marko Rößler and Ulrich Heinkel |
| 13:45 | - | 14:15 | Modulare Verifikation von Non-Mainline Chip-Level Funktionen | Matteo Michel |
| 14:15 | - | 14:45 | Formale Verifikation von eingebetteter Software für das Betriebssystem Contiki unter Berücksichtigung von Interrupts | Thilo Voertler, Benny Höckner, Petra Hofstedt and Thomas Klotz |
| 14:45 | - | 15:15 | Towards Verification of Artificial Neural Networks | Karsten Scheibler, Leonore Winterer, Ralf Wimmer and Bernd Becker |
| 15:15 | - | 15:45 | Kaffeepause |
| 15:45 | - | 18:00 | Session 2 |
| 15:45 | - | 16:15 | SpecScribe – ein pragmatisch einsetzbares Werkzeug zum Anforderungsmanagement | Chris Drechsler, Matthias Sauppe, Christian Pätz and Ulrich Heinkel |
| 16:15 | - | 16:45 | A Counterexample-Guided Approach to Symbolic Simulation of Hybrid Systems | Xian Li and Klaus Schneider |
| 16:45 | - | 17:15 | Evaluation of a software-based centralized Traffic Management inside run-time reconfigurable regions-of-interest of a mesh-based Network-on-Chip topology | Philipp Gorski, Tim Wegner and Dirk Timmermann |
| 17:15 | - | 17:45 | Ein Verfahren zur Bestimmung eines Powermodells von Xilinx MicroBlaze MPSoCs zur Verwendung in Virtuellen Plattformen | Sören Schreiner, Kim Gruettner, Sven Rosinger and Wolfgang Nebel |
| 17:45 | - | 18:00 | Modeling Power Consumption for Design of Power- and Noise-Aware AMS Circuits | Xiao Pan, Javier Moreno and Christoph Grimm |
| 18:00 | - | 18:30 | Fachgruppensitzung |
| 18:00 | - | 18:30 | Pause/Anreise SMAC |
| 18:30 | | | Abendveranstaltung |
Mittwoch, 04. März 2015
| Zeit | MBMV | Parallel |
|---|
| 08:30 | - | 09:00 | Anreise/Empfang |
| 09:00 | - | 09:45 | Using SystemVerilog UVM to build up an easy to use framework for a modular, reusable verification environment to enhance Block-/Subsystem- and System-Level verification closure
Keynote 2 | Markus Goertz |
| 09:45 | - | 10:00 | Kaffeepause |
| 10:00 | - | 12:00 | Session 3 | GPZV |
| 10:00 | - | 10:30 | Architectural System Modeling for Correct-by-Construction RTL Design | Joakim Urdahl, Dominik Stoffel and Wolfgang Kunz |
| 10:30 | - | 11:00 | On the Influence of Hardware Design Options on Schedule Synthesis in Time-Triggered Real-Time Systems | Alexander Biewer, Peter Munk, Jens Gladigau and Christian Haubelt |
| 11:00 | - | 11:30 | Symbolic Message Routing for Multi-Objective Optimization of Automotive E/E Architecture Component Platforms | Sebastian Graf, Michael Glass and Jürgen Teich |
| 11:30 | - | 12:00 | Model-based Systems Engeneering with Matlab/Simulink in the Railway Sector | Alexander Nitsch, Benjamin Beichler, Frank Golatowski and Christian Haubelt |
| 12:00 | - | 13:15 | Mittagspause |
| 13:15 | - | 15:30 | Session 4 | GINKO |
| 13:15 | - | 13:45 | A new Mapping Method from Fuzzy Logic System into Fuzzy Automaton | Lei Yang, Erik Markert and Ulrich Heinkel |
| 13:45 | - | 14:15 | Framework for Varied Sensor Perception in Virtual Prototypes | Stefan Mueller, Dennis Hospach, Joachim Gerlach, Oliver Bringmann and Wolfgang Rosenstiel |
| 14:15 | - | 14:45 | HOPE: Hardware Optimized Parallel Execution | Aquib Rashid, Arne Zender and Wolfram Hardt |
| 14:45 | - | 15:00 | Execution Tracing of C Code for Formal Analysis | Heinz Riener, Michael Kirkedal Thomsen and Goerschwin Fey |
| 15:00 | - | 15:15 | Verbesserung der Fehlersuche in Inkonsistenten Formalen Modellen | Nils Przigoda, Robert Wille and Rolf Drechsler |
| 15:15 | - | 15:30 | Deriving AOC C-Models from D&V Languages for Single- or Multi-threaded Execution using C or C++ | Tobias Strauch |
| 15:30 | | | Ende |